1. Field of the Invention
The present invention relates to the selective etching of metals, particularly the selective etching of TiW in microelectronics fabrication of capture pads for C4 solder bumps on electronic components.
2. Description of Related Art
Forming an electronic package assembly whereby an electrical component such as an integrated circuit chip is electrically and mechanically connected to a substrate, a card, or board, another chip or another electronic part is well-known in the art. This technology is generally termed surface mount technology (SMT) and has gained acceptance as the preferred means of making electronic package assemblies. The interconnect technology is known as ball grid array packaging, C4 flip chip interconnect, multi-chip modules, multilayer and micro via printed wiring boards and surface mount hybrid assembly. In one particular application, to which this application is directed to for convenience, a chip is electrically joined to a multilayer glass-ceramic electronic component and/or an organic substrate.
Multilayer glass-ceramic electronic components are typically joined to other components by soldering pads on a surface of one of the electronic components to corresponding soldering pads on the surface of the other component. Control Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wirebonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, an integrated circuit chip is mounted above a glass-ceramic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps to form an electronically connected module. A module is typically connected to other electronic components by solder or socket type connections.
In the C4 interconnect technology a relatively small solder hump is attached to the pads on one of the components being joined, typically to the chip. The electrical and mechanical interconnects are then formed by positioning the corresponding pads on the glass-ceramic substrate to be joined adjacent the solder humps on the chip and reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip bump pattern to the corresponding pads on the glass-ceramic substrate.
A myriad of solder structures have been proposed for the surface mounting of one electronic component to another. Typical surface mount processes form the solder structures by screening solder paste on conductive, generally metallic pads exposed on the surface of a chip or substrate. The solder paste is reflowed in an inert atmosphere and wets the pad and brings the solder into a spherical shape. After alignment of corresponding pads the whole assembly goes through a reflow operation to form solder bonds. The interconnection made by joining components by an array of solder balls is termed a ball grid array (BGA). When the solder structure is in the form of a column, it is termed a column grid array (CGA). Land grid array (LGA) interconnection is used in socket type electronic assemblies.
In C4 technology the solder bumps ate formed directly on the metal pads of the one unit. The pads are electrically isolated from other pads by the insulating substrate that surrounds each pad. The substrate might be un-doped silicon (Si) or some other material. The bottom of the pad is electrically connected into the chip or substrate circuit.
A major application of C4 is in joining semiconductor microchips (integrated circuits) to chip packages. Chips usually are made in rectangular arrays on a mono-crystalline slab of silicon called a “wafer,” which is a thin disc several inches across. Many chips are formed on each wafer, and then the wafer is diced into individual chips aid the chips are “packaged” in units large enough to be bandied. The C4 bumps are placed on the chips while they are still joined in a wafer.
C4 solder bumps must be mechanically well-fastened to their pads, or they may be torn off when the two surfaces are pushed together for electronical connection. It will be appreciated that a complex device such as a computer may have dozens of chips and hundreds or thousands of C4 solder ball connections, and the entire device may be rendered useless if only one of the bumps fails. The attachment of the C4 bumps requires careful design.
One method of forming solder bumps uses sputtering or vacuum deposition. Solder metal is evaporated in a vacuum chamber and the metal vapor coats everything in the chamber with a thin film of the evaporated metal. To form solder bumps on the substrate, the vapor is allowed pass through holes in a metal mask held over the substrate. The solder vapor passing through the holes condenses onto the cool surface into solder bumps. This method requires a high vacuum chamber to hold the substrate, mask, and flash evaporator.
An alternative technique for making solder bumps is electrodeposition, also called electrochemical plating or electroplating. This method also uses a mask such as patterned photoresist and forms solder bumps only at the selected sites.
Solder bump electrodeposition requires a first preliminary step, the creation of a continuous “seed layer” of conductive metal adhered onto a barrier layer on the insulating substrate. The seed layer is needed to deposit solder.
The second preliminary step, after the seed layer is laid down, is to form a mask by photolithography. A metal mask may also be used. For the photolithography method, a layer of photoresist is laid onto the seed layer and exposed to light. Unexposed photoresist can then be washed away to leave the cured photoresist behind as a mask.
When the exposed photoresist has been cured and the uncured photoresist has been removed, the mask is complete. The mask has rows of holes where the solder bumps are to be deposited.
The third step is preferably electrodeposition (electroplating) of copper to form a conductive pad and then to deposit metal alloy into the mask holes containing the copper pads. Solder can be directly deposited on the copper seed layer hut this is not preferred.
After the solder bumps are formed, the mask of cured photoresist is removed. The substrate now is covered with the continuous seed layer, copper pad, and numerous solder bumps on the copper pads. The seed layer between the solder bumps must now be removed to electrically isolate them. The removal can be done by chemical etching or by electroetching.
Capture pads for C4 bumps on semiconductor wafers for injection molded solder (IMS) transfer are preferably made by a through resist plating of Ni or Cu/Ni pads onto a Cu seed layer, it is also preferred to use a conductive barrier layer on the substrate surface and the Cu seed layer is preferably made by sputtering of Cu onto a sputtered TiW layer. After plating and resist stripping steps the Cu seed layer and TiW layer around capture pads need to be removed. The Cu seed layer can be removed by a conventional wet etch step. However, etching of exposed TiW layer around capture pads needs to be addressed since the complete removal of the TiW layer is important to eliminate shorts between bumps and is difficult to perform in the art.
An alternate method for preparing capture pads is to sputter layers of seed metal on to the substrate surface and using patterned photoresist and etching to form the capture pads. Cu seed layer is made by sputtering Cu onto a sputtered Ni, or NiCu alloy, on to a sputtered TiW layer. After resist application and develop, the capture pads are formed by etching Cu, Ni (or NiCu alloy), and TiW in the presence of resist. The Cu seed layer can be removed by a conventional wet etch, step, as is the Ni or NiCu alloy. Etching of exposed TiW layer is critical since residual TiW results in shorts between bumps.
The TiW etch chemistry used for etching of the TiW layer around C4 bumps convention ally consists of H2O2 (etchant), K2EDTA (bath stabilizer) and K2SO4 (corrosion protection for lead). This chemistry is used to etch TiW on wafers with electroplated C4 bumps with different solder composition (HTS, LTS, PbFree). Frequently, extensive TiW undercut is observed after the TiW etch step. It has been proposed that the undercut is caused by the presence of Cu in the BLM stack. It has been shown that having K2EDTA in the TiW etch bath greatly affects preferential TiW undercut. While K2EDTA presence can contribute to increased bath stability, it also accelerates Cu etch, thereby increasing concentration of Cu ions and accelerating TiW etch rate, causing TiW undercut.
Thus, it is an object of this invention to develop an etch chemistry for the removal of a TiW layer around capture pads, especially for C4NP wafers, which would not be sensitive to the presence of Cu in the BLM stack.
One solution to this problem is the use of a dry reactive ion etch (RIE) to remove the TiW layer. However, this technique is very sensitive to any surface contaminants including Cu residue that affects manufacturing yields.
U.S. Pat. No. 5,130,275 employs a barrier metal layer of 10% Ti and 90% W by weight coated over Al or gold (Au) interconnect pads and a passivating layer of SiO2. A Cu or Au seed layer is coated over the barrier layer.
The TiW barrier layer is etched in an aqueous solution of 30% hydrogen peroxide and it is noted that peroxide can corrode the solder bead atop the Cu/Au bump and teaches prevention of corrosion by adjusting the pH of the solution to between 9 and 11 (basic). The preferred solution is 7% ammonium persulfate and 1% to 2% hydrogen peroxide, with the pH adjusted to between 9 and 11 by adding ammonium hydroxide.
A 10% Ti-90% W barrier layer is also taught by James Watson in U.S. Pat. No. 5,041,191. Watson's TiW etchant is 5 g of cupric sulfate (Cu2SO4), 10 ml ammonium hydroxide (NH4OH), 100 ml glycerol, and 125 ml deionized water.
Stephen Pyke in U.S. Pat. No. 4,671,852, teaches a selective TiW etchant composed of 0.1 molar EDTA, 30% hydrogen peroxide, and concentrated ammonium hydroxide mixed in a respective volume ratio of 10:3:2. Pyke states that the pH should be less than 11 (not too basic).
U.S. Pat. No. 4,814,293, issued to Jacques Van Oekel, also teaches chemical etching of 10% Ti-90% W. It is noted that hydrogen peroxide causes inhomogeneous etching, and in particular, the undercutting or underetehing, when TiW films are layered between other metals is irregular. The agitation commonly used is ineffective in reducing the uneven results, and the patent advocates stagnant liquid etchants. Van Oekel buffers the peroxide solution to a pH value between 1 and 6 (acidic) and the preferred buffering compounds are acetic acid and ammonium acetate. Citric acid and sodium hydroxide may also be used. The etch rate is varied with the pH.
Minford et al., in U.S. Pat. No. 4,554,050 teach the use of Ti etchants in fabricating waveguides and the etchant is composed of EDTA, water, hydrogen peroxide, and ammonium hydroxide. The pH is about 10. The etch rate is controlled by varying the OH concentration and the temperature.
Bearing in mind the deficiencies of the prior art it is an object of the present invention to provide an etchant composition for selectively etching a barrier layer such as TiW in the presence of other metals, such as Cu, Ni, CuNi, NiCu, used in the fabrication of microelectronic components such as Cu solder pad fabrication.
It is another object of the present invention to provide a method for selectively etching a barrier layer such as TiW in the fabrication of microelectronic components such as C4 solder pad fabrication.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.